1. Field of the Invention
The present invention relates generally to synchronous semiconductor memory devices operating in synchronization with a clock signal, and more particularly to a logic-merged synchronous semiconductor memory device integrated with a processor or a logic circuit on the same semiconductor chip. More specifically, the present invention relates to the configuration of a data input/output circuit for a logic-merged synchronous semiconductor memory device.
2. Description of the Background Art
FIG. 20 is a schematic diagram of the general configuration of a conventional clock synchronous semiconductor memory device. In FIG. 20, the conventional clock synchronous semiconductor memory device includes memory arrays 1a to 1d each having a plurality of memory cells arranged in a matrix of rows and columns, pre-amplifier circuits 2a to 2d provided corresponding to memory arrays 1a to 1d to amplify and latch data in a selected memory cell in a corresponding memory array, a latch circuit 3 coupled in common to pre-amplifier circuits 2a to 2d through an internal read data bus RDF to latch data transferred from pre-amplifier circuits 2a to 2d, and an output circuit 4 coupled to latch circuit 3 through a data bus RD to buffer data transferred from latch circuit 3 for external output. Pre-amplifier circuits 2a to 2d each include pre-amplifiers to amplify 16-bit selected memory cell data received from corresponding memory arrays 1a to 1d through global data lines GIO0 to GIO3 and latches to latch the data amplified by the pre-amplifiers. The latches included in pre-amplifier circuits 2a to 2d (first stage latches) respectively transmit data latched according to transfer instruction signals OES0 to OES3 from a control circuit 5 onto internal read data bus RDF.
Output circuit 4 includes a latch coupled to latch circuit 3 through 16-bit internal data bus RD for latching 16-bit data from latch circuit 3, and an output buffer to buffer data held by the latch for external output. The latch in output circuit 4 latches and outputs 16-bit data transferred from latch circuit 3 according to a transfer instruction signal CLKOE from control circuit 5. Control circuit 5 generates instruction signals OES0 to OES3 and signal CLKOE in synchronization with an internal dock signal CLK, when data is read out.
Memory arrays 1a to 1d constitute banks #0 to #3, respectively, and control circuit 5 activates/inactivates these banks #0 to #3 independently from each other. Herein, the "activation" of a bank refers to the state where a word line is held in a selected state, and memory cell data connected to the selected word line is latched by a sense amplifier. The operations of the clock synchronous semiconductor memory device shown in FIG. 20 will be now described referring to a timing chart in FIG. 21.
In a clock cycle #a, a read command to instruct a data reading operation is applied. Herein, the command is applied as a combination of the states of a plurality of control signals. Control circuit 5 incorporates the read command at a rising edge of internal clock signal CLK and identifies the instruction of data reading. An address signal ADD(A) to address a memory cell to access and a bank address BA specifying a bank to be accessed are applied simultaneously with the application of the read command. Control circuit 5 starts a memory column selecting and data reading operation to bank (#0) addressed according to bank address BA and address signal ADD(A).
When bank #0 is selected, 16-bit memory cells are selected in a memory array 1a, and data in the 16-bit memory cells is transferred to a pre-amplifier circuit 2a through global data bus GIO0. The data latched by pre-amplifier circuit 2a is transferred to internal read data bus RDF according to transfer instruction signal OES0 and latched in latch circuit 3. Subsequently, latch circuit 3 transfers the latched data, according to a control signal RDGATE from control circuit 5, to output circuit 4 through internal data bus RD.
Output circuit 4 latches and outputs the data applied from latch circuit 3 according to an output control signal CLKOE. Instruction signals OES0, RDGATE and CLKOE are activated in synchronization with internal clock signal CLK. A certain clock cycle(s) is necessary for transferring data from pre-amplifier circuit 2a to output circuit 4. Therefore, first data a0 from output circuit 4 is output in clock cycle #c, and first data a0 is defined and sampled by an external device at a rising edge of clock signal CLK in clock cycle #d. The number of clock cycles required since the application of the read command until valid data is output is called CAS latency.
Control circuit 5 sequentially generates address signals with the first address ADD(A) being a head address and controls a column selecting operation to be executed in a selected bank in each clock cycle. The number of pieces of data which can be sequentially read out when a single read command is applied is called burst length. In FIG. 21, a data reading operation when the burst length is 4 is shown. Data a1, a2, and a3 are sequentially read out in synchronization with clock signal CLK in clock cycles #d, #e, and #f respectively.
In reading data from bank #0 (memory array 1a), a read command is once again applied in clock cycle #e to specify another bank. In FIG. 21, bank address BA specifies bank #1 by way of illustration. By the read command to bank #1, control circuit 5 executes a memory cell column selecting operation in memory array 1b, and sequentially reads out data through pre-amplifier circuit 2b. In bank #1, the CAS latency in the data reading operation is also 3. Therefore, after the final data a3 is transferred from memory array 1a (bank #0) to output circuit 4, the first data b0 is transferred from bank #1 through pre-amplifier circuit 2b to latch circuit 3 and latched therein, and output through output circuit 4 in clock cycle #g. In clock cycles #h and #i, data b0 and b1 read out from bank #1 are sequentially defined.
As described above, memory arrays 1a to 1d are formed in the bank-configuration and activated independently from each other and one bank is accessed while another bank is accessed to read memory cell data, data may be serially read out, which permits high-speed accessing operations.
Furthermore, by applying an active command ACT to one bank and selecting a word line while accessing another bank, time required for page switching may be hidden by the data accessing time, and data may be serially read out without otherwise generated penalty in page accessing.
Note that a power supply circuit 6a is provided between memory arrays 1a and 1c, and a power supply circuit 6b is provided between memory arrays 1b and 1d. These power supply circuits 6a and 6b generate power supply Vcc, ground voltage GND, high voltage Vpp for driving a word line, substrate bias voltage Vbb, and the like. By providing one power supply circuit for each bank, the load of the power supply circuit is alleviated as compared to the case of driving all the memory arrays by one power supply circuit, so that necessary voltage may be stably supplied and stable operations may be secured. In particular, 16-bit pre-amplifiers and latches and output buffers operate in reading 16-bit data, relatively large current consumption results, and the required large current may be sufficiently secured and the data may be stably read out as a result.
FIG. 22 is a diagram specifically showing the configuration of a data reading portion in the clock synchronous semiconductor memory device shown in FIG. 20. FIG. 22 shows the configuration of a 1-bit data reading portion. In FIG. 22, pre-amplifier circuits 2a to 2d for banks #0 to #3 are coupled in common to internal read data bus lines RDFL and /RDFL. Pre-amplifier circuit 2a includes a pre-amplifier 2aa to amplify data in a selected memory cell, an inverter latch 2ab to latch the data amplified by pre-amplifier 2aa, and a transfer circuit 2ac to transfer the data latched by inverter latch 2ab to read data bus lines RDFL and /RDFL in response to transfer instruction signal OES0. Transfer circuit 2ac includes a tri-state buffer activated in response to transfer instruction signal OES0.
Pre-amplifier circuit 2b includes a pre-amplifier 2ba to amplify data in a selected memory cell in bank #1, an inverter latch 2bb to latch the data amplified by pre-amplifier 2ba, and a transfer circuit 2bc to transfer the data latched by inverter latch 2bb to internal read data bus lines RDFL and /RDFL in response to activation of transfer instruction signal OES1.
Pre-amplifier circuit 2c includes a pre-amplifier 2ca to amplify applied memory cell data, an inverter latch 2cb to latch the data amplified by pre-amplifier 2ca, and a transfer circuit 2cc to transfer the data latched by inverter latch 2cb to internal read data bus lines RDFL and /RDFL in response to activation of transfer instruction signal OES2.
Pre-amplifier circuit 2d includes a pre-amplifier 2da to amplify data in a selected memory cell in bank #3, an inverter latch 2db to latch the data amplified by pre-amplifier 2da, and a transfer circuit 2dc to transfer the data latched by inverter latch 2db to internal read data bus lines RDFL and /RDFL in response to activation of transfer instruction signal OES3. Transfer circuits 2bc to 2dc are each implemented by a tri-state buffer which in turn amplifies and outputs applied data when activated and enters a high impedance state when inactivated.
Pre-amplifiers 2aa and 2da are activated in response to activation of pre-amplifier activation signals PAE0 to PAE3, respectively. Pre-amplifier activation signals PAE0 to PAE3 and transfer instruction signals OES0 to OES3 are each activated when a corresponding bank is a selected bank.
Latch circuit 3 includes a transfer gate 3a responsive to activation of transfer instruction signals RDGATE and /RDGATE for transferring data on internal data bus lines RDFL and /RDFL, and an inverter latch 3b which latches data transferred from transfer gate 3a. Transfer gate 3a includes a CMOS transmission gate provided to each of internal read data bus lines RDFL and /RDFL.
Output circuit 4 includes a transfer gate 4a to transfer a signal on the latch nodes RDL and /RDL of inverter latch 3b according to transfer instruction signals CLKOE and /CLKOE, an inverter latch 4b to latch the data on nodes RDL and /RDL transferred from transfer gate 4a, and a main amplifier 4c to amplify and externally output the data latched by inverter latch 4b through the output node. Transfer gate 4a includes a CMOS transmission gate provided for each of latch nodes RDL and /RDL. The operations of the reading portion of the clock synchronous semiconductor memory device shown in FIG. 22 will be now described referring to a timing chart in FIG. 23. Note that FIG. 23 show a data reading operation where the burst length is 1 and the CAS latency is 3.
A read command is applied in clock cycle #a, and simultaneously applied bank address BA specifies bank #0. In bank #0, a column selecting operation is performed according to address signal ADD(A), selected memory cell data is transferred to pre-amplifier 2aa, then pre-amplifier activation signal PAE0 is activated, and pre-amplifier 2aa amplifies the memory cell data. Inverter latch 2ab latches the data amplified by pre-amplifier 2aa.
A read command is again applied in clock cycle #b, and simultaneously applied bank address BA specifies bank #1. In bank #1 a column selecting operation is performed according to simultaneously applied address signal ADD(B), and selected memory cell data is transferred to pre-amplifier 2ba. Pre-amplifier activation signal PAE1 is then activated, pre-amplifier 2ba amplifies the memory cell data and inverter latch 2bb latches the data amplified by pre-amplifier 2ba.
In this clock cycle #b, a transfer instruction signal OES0 is activated in synchronization with a rising of clock signal CLK, and in bank #0, transfer circuit 2ac is activated to transfer data Q0 latched by inverter latch 2ab to internal read data bus lines RDFL and /RDFL.
In this clock cycle #b, data transfer instruction signal RDGATE is activated in synchronization with a rising of clock signal CLK, which turns on transfer gate 3a, and data Q0 transferred onto internal read data bus lines RDFL and /RDFL is transferred to inverter latch 3b. Inverter latch 3b latches data Q0 applied through transfer gate 3a.
In clock cycle #c, transfer instruction signal OES1 is activated in synchronization with a rising of clock signal CLK, and transfer circuit 2bc for bank #1 is activated to transfer data latched by inverter latch 2bb in clock cycle #b to internal read data bus lines RDFL and /RDFL. In this clock cycle #c, transfer instruction signal CLKOE attains an H level in synchronization with a rising of clock signal CLK, which turns on transfer gate 4a, and main amplifier 4c amplifies the data applied through transfer gate 4a for external output. Before transfer instruction signal CLKOE falls to an L level, transfer instruction signal RDGATE is activated in response to a rising of clock signal CLK, and memory cell data Q1 transmitted onto internal read data bus lines RDFL and /RDFL is transferred, and inverter latch 3b latches data Q1 applied through transfer gate 3a. A certain time period is necessary for the data transfer, during which period transfer instruction signal CLKOE attains an L level before the data in inverter latch 3b is defined, and the unstable data (Q1) is prevented from being output.
In clock cycle #d, transfer instruction signal CLKOE is again activated in synchronization with a rising of clock signal CLK, which turns on a transfer gate 4a, and the data latched by inverter latch 3b is externally transmitted through main amplifier 4c. Data Q0 and Q1 are defined at a rising of clock signal CLK in clock cycles #d and #e, respectively and sampled by an external processor or the like.
As shown in FIG. 23, the transfer instruction signal is consecutively activated in synchronization with clock signal CLK and data is transferred from the pre-amplifier circuit through the internal data read bus, and transfer circuit 3 to output circuit 4 in a pipeline manner, and therefore while a long period of time is necessary for the data to be transferred from one bank to an outside of the device (3 clock cycles in FIG. 23), the data can be serially read out once the data starts to be read out, so that high-speed data reading is achieved.
Note that although the burst length in the data reading in FIG. 23 is 1, the burst length may be 4, 8 or the like.
As shown in FIG. 24, let us now assume that a clock synchronous semiconductor memory device (SDRAM: Synchronous Random Access Memory) 102 and a processor or application specific logic circuit (hereinafter collectively referred to as "logic") 104 are integrated on a semiconductor chip 100. Clock synchronous semiconductor memory device (SDRAM) 102 and logic 104 are coupled through an internal data bus 106. As clock synchronous semiconductor memory device (SDRAM) 102, the clock synchronous semiconductor memory device shown in FIG. 20 is applied. In this case, output circuit 4 in FIG. 20 is coupled to data bus 106. Output circuit 4 in FIG. 20 outputs 16-bit data. In order to increase the bandwidth in data transfer between clock synchronous semiconductor memory device 102 and logic 104, the bus width of internal data bus 106 is for example expanded to 256 bits to 1024 bits. Since clock synchronous semiconductor memory device (SDRAM) 102 and logic 104 are integrated on semiconductor chip 100, the lead pitch condition for pin terminals may be placed out of consideration, and therefore internal data bus 106 may be provided along the pitch of the internal interconnections, which expands the bus width. In this case, however, applying the configuration of the clock synchronous semiconductor memory device shown in FIG. 20 as it is gives rise to the following problem.
Let us now assume that output circuit 4 outputs 256-bit data as shown in FIG. 25. More specifically, internal data bus 106 shown in FIG. 24 has a bus width of 256 bits. In this case, data bus RD between output circuit 4 and latch circuit 3 has a bus width of 256 bits. Two-bank configuration where memory arrays 1a and 1b constitute bank #0 and memory arrays 1c and 1d constitute bank #1 is now considered. In this case, global data buses GIO0 to GIO3 respectively in memory arrays 1a to 1d each have a bus width of 128 bits. Meanwhile, internal read data bus RDF coupled in common to pre-amplifier circuits 2a to 2d has a bus width of 256 bits. Global data buses GIO0 to GIO3 at uppermost interconnections in the arrays can have their bus widths expanded relatively easily. However, if the bus widths of internal read data bus RDF and bus RD are expanded to 256 bits, these internal data bus RDF and data bus RD must be provided among the memory arrays, which increases the area occupied by the buses and the area of the chip accordingly. If the bus width of internal data bus 106 shown in FIG. 24 is expanded to 1024, for example, the bus widths of internal read data bus RDF and data bus RD increase and the area of the chip increases as well.
In particular, if the read data bus to transmit reading data and the write data bus to transmit writing data are separately provided, the area occupied by buses is further increased, which increases the area of the chip.